The present invention is directed to semiconductor devices and, more specifically, to semiconductor devices including thyristor-based devices.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-die microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small semiconductor device packages. The improvements in such devices has led to a dramatic increase in their use in a variety of applications. As the use of these devices has become more prevalent, the demand for reliable and affordable semiconductor devices has increased. Accordingly, the need to manufacture such devices in an efficient and reliable manner has become increasingly important.
An important part in the circuit design, construction, and manufacture of semiconductor devices concerns semiconductor memories; the circuitry used to store digital information. Conventional random access memory devices include a variety of circuits, such as SRAM and DRAM circuits. The construction and formation of such memory circuitry typically involves forming at least one storage element and circuitry designed to access the stored information.
Various SRAM cell designs based on NDR (Negative Differential Resistance) devices have been proposed in the past. These designs typically consist of at least two active elements, including an NDR device. The NDR device is important to the overall performance of this type of SRAM cell. A variety of NDR devices have been introduced ranging from a simple bipolar transistor to complicated quantum-effect devices. One advantage of the NDR-based cell is the potential of having a cell area smaller than 4T (four transistor) and 6T (six transistor) SRAM cells because of the smaller number of active devices and interconnections. Conventional NDR-based SRAM cells, however, have many problems that have prohibited their use in commercial SRAM products. Some of these problems include: high standby power consumption due to the large current needed in one or both of the stable states of the cell; excessively high or excessively low voltage levels needed for the cell operation; stable states that are too sensitive to manufacturing variations and provide poor noise-margins; limitations in access speed due to slow switching from one state to the other; limitations in operability due to temperature, noise, voltage and/or light stability; and manufacturability and yield issues due to complicated fabrication processing.
NDR devices including thyristors are also widely used in power switching applications because the current densities carried by such devices can be very high in their on state. Additionally, in a thin capacitively coupled thyristor device, a base region is capacitively coupled to a control port, such as a gate. This capacitive coupling enhances the switching of the thyristor between the blocking state and conducting state. An important aspect of a thin capacitively-coupled thyristor device is that the body of the thyristor is thin enough so that the capacitive coupling between the control port and the thyristor base region can substantially modulate the potential of the base region. Because of this, the manufacture of the thin capacitively-coupled thyristor device can be difficult.
The above-mentioned difficulties associated with the formation of thyristor-based devices have presented and continue to present challenges to the manufacture and implementation of such devices.
The present invention is directed to thyristor-based devices that address the above-mentioned challenges. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a semiconductor device includes a thyristor having an extended portion that capacitively couples a portion of a control port (e.g., a gate) to the thyristor. The thyristor includes at least two contiguous regions of different polarity, a first one of the contiguous regions having a portion in a current path extending between two other regions of the thyristor and having an extended portion outside the current path and extended from the thyristor. A conductive structure faces the extended and/or the current path portions of the first one of the contiguous regions and is capacitively coupled to the extended and/or current path portions. The conductive structure is adapted to control the thyristor via the capacitive coupling. In this manner, the extended portion increases the capacitive coupling to the thyristor, addressing challenges including those discussed above.
According to another example embodiment of the present invention, a memory cell having a thin capacitively coupled thyristor thin capacitively-coupled thyristor has an extended portion from the thyristor that capacitively couples a gate to the thin capacitively-coupled thyristor. The thin capacitively-coupled thyristor includes a body having an anode (e.g., a P+ emitter region) a N-doped base region, a P-doped base region and a cathode (e.g., an N+ emitter region). One or both of the base regions has a portion that extends outside of a current path extending between the other base region and the emitter adjacent to the first base region of the thyristor. A gate dielectric is formed on the base region with an extended portion, and a control gate is formed on the gate dielectric. The control gate is capacitively coupled to the base region with the extended portion via the gate dielectric and adapted to control the thyristor via the capacitive coupling. A pass gate transistor having a gate and two source/drain regions is electrically coupled via one of the source/drain regions to one of the emitter regions.
In another example embodiment of the present invention, the surface area of the base region is increased, for example, by roughening and/or adding texture to the surface. The control port is capacitively coupled to the base region via the roughened and/or textured surface, which increases the capacitive coupling between the control port and the base region.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.